The present invention, relates to semiconductor devices and methods of fabricating the same and, more particularly, to self-aligned contact structures in semiconductor devices and methods of forming the same.
As semiconductor devices become more highly integrated, separation space between interconnection lines decreases. As the separation space between interconnection lines decreases, there is an increase in the probability that misalignments will occur when defining contact holes using photolithography techniques. These contact holes usually penetrate an interlayer insulating layer that exists between interconnection lines that are disposed parallel to each other. A self-aligned contact (SAC) technology recently has been proposed in order to address this misalignment problem.
Conventional SAC technology usually includes forming a plurality of interconnection lines covered with an insulating layer, such as a silicon nitride layer, on a semiconductor substrate. An interlayer insulating layer, such as a silicon oxide layer, typically is then formed over the entire surface of the resultant structure having the plurality of interconnection lines, and thereafter a predetermined region of the interlayer insulating layer that exists between the interconnection lines is etched using the insulating layer formed of the silicon nitride layer as an etching mask. This process forms self-aligned contact holes that expose the semiconductor substrate.
Although though the width of the self-aligned contact holes is wider than the space between the adjacent interconnection lines, this process can prevent the interconnection lines from being exposed by the self-aligned contact holes. This is because the interconnection lines are surrounded by a silicon nitride layer (e.g., insulating layer) having an etching selectivity with respect to the interlayer insulating layer formed of silicon oxide. Accordingly, the misalignment margin is increased during performance of the photolithography process that defines the self-aligned contact holes.
However, the dielectric constant of the silicon nitride layer is higher than that of the silicon oxide layer. Thus, the coupling capacitance, that is, the parasitic capacitance between the interconnection lines and the conductive layer that is used to fill in the self-aligned contact hole, is increased, which in turn degrades the electrical characteristics of the semiconductor device. In addition, in the conventional SAC technology described above, the interconnection lines may be formed of a metal layer, (such as a tungsten layer), or a metal polycidie layer, (such as a tungsten polycide layer), in order to reduce the resistance of the interconnection lines. The metal interconnection lines typically are formed by patterning the metal layer or the metal polycide layer. A bridge may exist, however, between the adjacent interconnection lines during performing the photolithography and etching processes that are used to pattern the metal layer due to the rough surface morphology of the metal layer. Therefore, the adjacent interconnection lines may be electrically connected to each other.
A multi-level interconnection structure fabricated by a dual damascene technology is described in U.S. Pat. No. 5,614,765 entitled xe2x80x9cSelf-aligned via dual damascenexe2x80x9d by Avazino et al., the disclosure of which is incorporated herein by reference in its entirety. According to U.S. Pat. No. 5,614,765, an interlayer insulating layer having a groove and a via hole exposing an underlying interconnection is formed on a substrate, and an upper interconnection is formed to fill the groove and the via hole. Here, the via hole and the groove are formed through one photolithography process.
Forming the groove in accordance with the above-mentioned patent includes forming a photoresist pattern on the interlayer insulating layer, and then etching the interlayer insulating layer to a depth shallower than the thickness of the interlayer insulating layer by using the photoresist pattern as an etching mask. The groove now will include a via portion and a conductive line portion, where the via portion is wider than the conductive line portion. Also, the via hole formation process includes forming a conformal material layer over the entire surface of the resultant structure having the groove. The conformal material layer then is anisotropically etched to form a spacer on a sidewall of the groove, and the interlayer insulating layer is selectively etched in the via portion to expose the underlying interconnection. Here, the conformal material layer should be thinner than half of the width of the via portion, and it should be thicker than half of the width of the conductive line portion. Thus, after forming the spacer, the bottom of the via portion is exposed, and the bottom of the conductive line portion is covered with the spacer.
U.S. Pat. No. 5,614,765 therefore describes the presence of a via hole interposed between the underlying interconnection and the upper interconnection. Notwithstanding such self-alignment techniques, there continues to be a need for improved methods of forming self-aligned contact holes penetrating the interlayer insulating layer between adjacent interconnections.
It is therefore a feature of an embodiment of the present invention to provide semiconductor devices having self-aligned contact holes. Another feature of an embodiment of the present invention is to provide self-aligned contact structures in semiconductor devices as well as a method of forming self-aligned contact structures that can minimize the parasitic capacitance between a conductive layer pattern filled in the self-aligned contact hole, and the interconnection adjacent to the self-aligned contact hole. It is another feature of an embodiment of the present invention to provide a method of forming a self-aligned contact hole structure that can increase over etching process margins during performance of the etching process that forms the self-aligned contact holes that penetrate the interlayer insulating layer between adjacent interconnections. It is yet another feature of an embodiment of the present invention to provide a method of forming a self-aligned contact hole structure that is capable of easily patterning the interconnections adjacent to the self-aligned contact hole.
In accordance with these and other features of various embodiments of the present invention, there is provided a self-aligned contact structure in a semiconductor device, comprising a semiconductor substrate having active regions, an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region, at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x), a mask pattern having a top portion of width (z) and a bottom portion of width (y) formed on each interconnection, and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein xxe2x89xa6yxe2x89xa6z and x less than z. In a preferred embodiment of the present invention, each active region comprises a conductive pad. In another preferred embodiment of the present invention, the second interlayer insulating layer has a dielectric constant that is lower than the dielectric constant of the mask pattern. In another preferred embodiment of the present invention, the interconnections comprise a barrier metal layer and an interconnection metal layer that are sequentially stacked. In another preferred embodiment of the present invention, the interconnections comprise an interconnection metal layer having a bottom and sidewalls and a barrier metal layer surrounding the bottom and sidewalls of the interconnection metal layer. In another preferred embodiment of the present invention, the mask pattern comprises an etch stop layer pattern having sidewalls formed on the interconnection and a first spacer having inner and outer sidewalls formed on the sidewalls of the etch stop layer pattern, the outer sidewall of the first spacer having a vertical profile that is perpendicular to the top surface of the semiconductor substrate. In another preferred embodiment of the present invention, the self-aligned contact structure in a semiconductor device of the present invention further comprises a second spacer interposed between the conductive layer pattern and the first spacer. In another preferred embodiment of the present invention, the mask pattern comprises an etch stop pattern having a vertical sidewall profile that is perpendicular to the top surface of the semiconductor substrate. Preferably, the interlayer insulating layer is made of silicon oxide.
In accordance with a feature of another embodiment of the present invention, there is provided a method of forming a self-aligned contact hole structure in a semiconductor device. In accordance with a feature of a preferred embodiment of the present invention, there is provided a method of forming a self-aligned contact structure in a semiconductor device, comprising providing a semiconductor substrate having active regions, forming an interlayer insulating layer on the semiconductor substrate, forming at least two parallel interconnections on the interlayer insulating layer, at least one active region being disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x), forming a mask pattern having a top portion (z) and a bottom portion (y) on each interconnection; and forming a conductive layer pattern, penetrating at least a portion of the interlayer insulating layer that is exposed between the mask pattern, that is electrically connected to at least one active region, whereby xxe2x89xa6yxe2x89xa6z and x less than z.
In accordance with a feature of another embodiment of the present invention, the interlayer insulating layer on the semiconductor substrate is a first interlayer insulating layer, and forming the at least two parallel interconnections comprises sequentially forming a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer and a third etch stop layer on the first interlayer insulating layer, successively patterning the third etch stop layer, the third interlayer insulating layer and the second etch stop layer to form a first recessed region having at least a sidewall, and a second recessed region having at least a sidewall, each of the first and second recessed regions being substantially parallel to each other, forming a first spacer on the sidewalls of the first and second recessed regions, successively etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the first spacer as etching masks to form a first interconnection groove and a second interconnection groove, and forming a first interconnection and a second interconnection in the first interconnection groove and in the second interconnection groove respectively. The first to third interlayer insulating layers are preferably formed of an insulating layer having an etch selectivity with respect to the first to third etch stop layers and the first spacer. The first to third interlayer insulating layers are preferably formed of an insulating layer having a dielectric constant which is lower than the dielectric constant of the first to third etch stop layers and the first spacer. Forming the mask patterns preferably comprises forming a fourth etch stop layer over the surface of the resultant structure having the first and second interconnections, and filling the first and second recessed regions, and successively blanket-etching the fourth etch stop layer and the third etch stop layer until the third interlayer insulating layer is exposed, thereby forming fourth etch stop layer patterns in the respective first and second recessed regions, wherein the fourth etch stop layer patterns and the first spacer formed on sidewalls thereof constitute the mask pattern. Preferably, the fourth etch stop layer is comprised of the same material layer as the third etch stop layer. Preferably, forming the fourth etch stop layer patterns is followed by removing the exposed third interlayer insulating layer to expose a top surface of the second etch stop layer and a sidewall of the first spacer, forming a second spacer on the sidewall of the first spacer, and etching the second etch stop layer to expose the second interlayer insulating layer.
In another preferred embodiment of the present invention, forming the conductive layer preferably comprises successively anisotropic-etching the third interlayer insulating layer, the second etch stop layer, the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer using the mask patterns as etching masks to thereby form a contact hole exposing the conductive pad, forming a conductive layer over the surface of the resultant structure having the contact hole, filling the contact hole, and patterning the conductive layer. Preferably, the first to third etch stop layers, the fourth etch stop layer patterns, and the spacers are comprised of silicon nitride. Preferably, the third etch stop layer has a thickness greater than the total thickness of the first etch stop layer and the second etch stop layer.
In another preferred embodiment of the present invention, there is provided a method of forming a self-aligned contact structure in a semiconductor device, comprising providing a semiconductor substrate having active regions, forming a first interlayer insulating layer on the semiconductor substrate, forming a second interlayer insulating layer to form at least two parallel grooves on the first interlayer insulating layer, forming an interconnection in a lower portion of each groove, each interconnection having sidewalls, a bottom and a width (x), isotropically etching the second interlayer to increase the width of the exposed portion of each groove, forming a mask pattern having a top portion (z) and a bottom portion (y) in the exposed portion of each groove, and forming a conductive layer pattern, the conductive layer pattern penetrating at least a portion of the first and second interlayer insulating layers between the interconnections formed in the two parallel grooves, and being electrically connected to at least one active region, whereby xxe2x89xa6yxe2x89xa6z and x less than z.
In accordance with yet another preferred embodiment of the present invention, there is provided a method of forming a self-aligned contact structure in a semiconductor device, comprising providing a semiconductor substrate having at least one active region, forming a first interlayer insulating layer on the semiconductor substrate, forming at least two parallel interconnection patterns on the first interlayer insulating layer, at least one conductive pad being disposed between the at least two parallel interconnection patterns, each interconnection pattern having sidewalls, a bottom and width (x), forming a capping layer over the interconnection pattern, forming a second interlayer insulating layer, planarizing the second interlayer insulating layer until the top surface of the interconnection pattern is exposed, and etching the capping layer and the second interlayer insulating layer to form at least one recessed region in the second interlayer insulating layer, the recessed regions having a top portion of width (z) and a bottom portion of width (y) over the interconnection pattern, filling the recessed region with a masking material, forming a conductive layer pattern, the conductive layer pattern penetrating at least a portion of the first and second interlayer insulating layers between the interconnection pattern, and being electrically connected to the at least one active region, whereby xxe2x89xa6yxe2x89xa6z and are comprised of a metal layer, bridges are not left between the adjacent interconnections when the method of the invention is carried out.
While the present invention has been described in detail with reference to preferred embodiments, those skilled in the art will appreciate that various modifications may be made to the invention without departing from the spirit and scope thereof.
In accordance with an additional feature of an embodiment of the present invention, there is provided a method of forming a self-aligned contact structure in a semiconductor device. The method includes providing a semiconductor substrate, forming a first interlayer insulating layer, a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer and a third etch stop layer on the surface of the resultant structure having the conductive pad The method also includes successively patterning the third etch stop layer, the third interlayer insulating layer and the second etch stop layer to form a first recessed region having at least a sidewall, and a second recessed region having at least a sidewall, whereby each of the first and second recessed regions are substantially parallel to each other.
The method further entails forming spacers on the sidewalls of the respective first and second recessed regions, and successively etching the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the spacers as etching masks to form first and second interconnection grooves.
A first interconnection and a second interconnection then can be formed in the first interconnection groove, and in the second interconnection groove, respectively. Fourth etch stop layer patterns then can be formed in the respective first and second recessed regions, and the third etch stop layer concurrently removed. The method is completed by successively anisotropic-etching etching the third interlayer insulating layer, the second etch stop layer, the second interlayer insulating layer, the first etch stop layer and the first interlayer insulating layer using the spacers and the fourth etch stop layer patterns as etching masks to thereby form a contact hole exposing the conductive pad.
In accordance with an additional feature of another embodiment of the invention, there is provided a method of forming of forming a self-aligned contact structure in a semiconductor device that includes providing a semiconductor substrate, and forming a conductive pad on the semiconductor substrate. The method also includes sequentially forming a first interlayer insulating layer, a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer and a third etch stop layer on the surface of the resultant structure having the conductive pad. The third etch stop layer, the third interlayer insulating layer and the second etch stop layer can be successively patterned to form a first recessed region having at least a sidewall, and a second recessed region having at least a sidewall, whereby each of the first and second recessed regions are substantially parallel to each other.
The method also entails forming first spacers on the sidewalls of the respective recessed regions, and successively etching, the second interlayer insulating layer and the first etch stop layer using the third etch stop layer and the first spacers as etching, masks to form first and second interconnection grooves. A first interconnection and a second interconnection therein can be formed in the first interconnection groove, and in the second interconnection groove, respectively. Fourth etch stop layer patterns then can be formed in the respective first and second recessed regions, and the third etch stop layer concurrently removed. The method further includes removing the third interlayer insulating layer to expose sidewalls of the first spacers, forming second spacers on the exposed sidewalls of the first spacers, and etching the second etch stop layer that is present between the second spacers. The self-aligned contact can be completed by successively anisotropic-etching the second interlayer insulating layer, the first etch stop layer and the first interlayer insulating layer using the fourth etch stop layer patterns, the first spacers and the second spacers as etching masks, to thereby form a contact hole exposing the conductive pad.